1. Field of the Invention
The invention relates to an emitter coupled logic (ECL) circuit, and more specifically to an emitter coupled logic circuit, which combines metal oxidation semiconductor field effect transistors (MOSFETs) to provide a data reload function.
2. Description of the Related Art
Since the emitter coupled logic (hereinafter referred to as ECL) circuits may operate in high speed, the ECL circuits have been widely used in logic gate circuits, such as D-Type flip-flops. FIG. 1 shows an ECL circuit disclosed in U.S. Pat. No. 4,546,272, which is entitled “ECL circuit for forcibly setting a high level output”. The ECL circuit includes a pair of emitter coupled bipolar junction transistors TRI, TR2 and load resistors R1, R2 for receiving differential signals D and /D, a resistor RS, a current source, and a pair of bipolar junction transistors TR3, TR4. The resistor RS is connected to the emitters of the bipolar junction transistors TR1, TR2. The current source is connected to the resistor RS. The transistors TR3, TR4 are used for receiving a “set” S and “reset” R signals, respectively.
In the conventional ECL circuit, the resistor RS provides a voltage difference to make the base-emitter voltage difference (VBE3, VBE4) between the bipolar junction transistors TR3, TR4 greater than the base-emitter voltage difference (VBE1, VBE2) between the emitter coupled bipolar junction transistors TR1, TR2. Accordingly, the output signal can be forced to “set” or “reset” state.
The conventional ECL circuit provides the functions of “set” and “reset” other than the function of “reload”. Since the ECL circuit is not a logic digital circuit with complementary metal oxidation semiconductor (CMOS) transistors, the ECL circuit cannot directly receive the digital reload data as the “set” signal and “reset” signal. Therefore, when the digital reload data is needed, it is necessary to judge that the reload data is logic high H or logic low L. If the reload data is H, the “set” signal is set to a high voltage level, and the “reset” signal is set to a low voltage level. Adversely, if the data is L, the “set” signal is set to a low voltage level, and the “reset” signal is set to a high voltage level. Thus, the design is complicated. Furthermore, it needs time to convert the reload data into ECL voltage levels, therefore the data reload speed may be delayed and influences the data reload speed of the ECL circuit.